In an integrated circuit including MOS transistors, these transistors are generally produced from a single semiconductor layer in which the channels of these transistors are formed. This semiconductor layer is topped with metal interconnections forming contacts electrically connected to the gates and to the source and drain regions of the transistors.
In order to improve the integration density of the MOS transistors in the integrated circuits, it is known to produce integrated circuits including several stacked layers of transistors. One example of such an integrated circuit 1 is illustrated in FIG. 1. In this FIG. 1, only two transistors 3a and 3b, superimposed one on top of the other, of the integrated circuit 1 are illustrated. The upper transistor 3b is produced on a dielectric layer 5 covering the lower transistor 3a, which is itself realized on a dielectric layer 7, for example corresponding to the buried dielectric layer of a SOI (silicon on insulator) substrate. Each transistor 3a, 3b includes a semiconductor portion in which the source 9a, 9b and drain 11a, 11b regions are produced, as well as a region 13a, 13b designed to form the channel of the transistor 3a, 3b. A gate dielectric 15a, 15b topped with a gate 17a, 17b are arranged on the channel region 13a, 13b of each transistor 3a, 3b, the channel region 13a, 13b of each transistor 3a, 3b. Each stack formed by one of the gates 17a, 17b and one of the gate dielectrics 15a, 15b is surrounded by spacers 19a, 19b formed by one or several dielectric materials.
Relative to transistors produced from a single semiconductor layer, such a structure makes it possible to increase the integration density of the transistors in the integrated circuit. Moreover, such a structure makes it possible to modulate the electrical state of the interface between the region 13b designed to form the channel of the upper transistor 3b and the dielectric layer 5, or even, in the case of FD (fully depleted) transistors, to electrostatically couple the transistors that are superimposed on each other. Thus, in the example shown in FIG. 1, the gate 17a of the lower transistor 3a can serve to polarize the channel 13b of the upper transistor 3b, in particular owing to the small thickness of the dielectric layer 5, this thickness for example being less than about 50 nm, or less than about 30 nm or even 10 nm.
The effectiveness of such an electrostatic coupling is directly conditioned by the vertical alignment (alignment along the y axis shown in FIG. 1) between the gate 17a of the lower transistor 3a and the channel 13b of the upper transistor 3b. Thus, these two transistors 3a, 3b are correctly coupled in the case where the gate 17a of the lower transistor 3a is well aligned with the channel 13b of the upper transistor 3b, as is the case in FIG. 1. However, in the case where these elements are no longer correctly aligned in relation to each other, difficulties may then appear to polarize the channel 13b via the gate 17a. 
Such an integrated circuit 1 may be obtained by realizing the lower and upper levels (including the lower transistor 3a and the upper transistor 3b, respectively) separately, then assembling them together via the dielectric layer 5. It is, however, difficult to obtain, with this technique, a good alignment between the transistors of the different levels, the best results obtained making it possible to obtain an alignment in the vicinity of 100 nm.
In order to obtain a better alignment, it is preferable to manufacture the integrated circuit 1 by producing the different levels of transistors sequentially: one first produces the lower level including the lower transistor 3a, then one produces the upper level, including the upper transistor 3b, directly on the lower level by aligning the gate 17b of the upper transistor 3b in relation to the gate 17a of the lower transistor 3a during the lithography step implemented to realize said gate 17b. 
Although the alignment obtained with a sequential production of the levels of transistors is better than the alignment obtained by the separate production, then assembly of the levels of transistors, there is still an alignment uncertainty at least equal to about 40% of the minimum gate length (dimension along the x axis shown in FIG. 1) of the transistors.